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irmcf588 1 www.irf.com ? 201 5 international rectifier f ebruary 20 , 201 5 dual motor high p erformance sensorless control ic description irmcf588 is a high performance flash based motion control ic designed and optimized for complete air conditioner control which contains two kinds of computation engines integrated into one chip. there are two motion control engine s (mce tm ) for sensorless control of permanent magnet motors and the other is an 8 - bit high - speed microcontroller (8051). the user can program a m otion control algorithm by connecting these control elements using a graphic compiler. key components of the complex sensorless control algorithms, such as the angle estimator, are provided as complete pre - defined control blocks. a unique analog/digital ci rcuit and algorithm fully support s single shunt or leg shunt current reconstruction. irmc f588 performs a pfc (power factor correction) function in addition to the motor control. irmc f588 comes in a 100 pin qfp package . features ? dual mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? built - in hardware peripheral for single or two shunt current feedback reconstruction and op amp analog circuits ? integrated temperature sensor ? supports both interior and surface permanent magnet motor sensorless control ? zero speed sensorless control for ult ra - low speed operation ? dedicated pfc pwm for digital pfc control ? loss minimization space vector pwm ? five - channel analog output (pwm) ? embedded 8 - bit high speed microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for emulation/debugger ? two serial communication interface (uart) ? i2cserial interface ? watchdog timer with independent internal clock ? internal 64 kbyte flash plus 16kbyte otp memory ? 3.3v single supply ? factory calibrated analog inputs product summary maximum cloc k input (f crystal ) 60 mhz maximum internal clock (sysclk) 120mhz maximum 8051 clock (8051clk) 30mhz sensorless control computation time 35 sec@100mhz mce tm computation data range 16 bit signed 8051 program flash 52kb 8051 /mce data ram 2 x 4kb mce program ram 2 x 12 kb mce program otp 16kb gatekill latency (digital filtered) 2 sec pwm carrier frequency 20 bits/ sys clk a/d input channels 15 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of digital i/o (max) 31 package (lead free) qfp100 typical 3.3v operati ng current 5 0 ma base part number package type standard pack orderable part number form quantity irmcf5 88 lqfp 100 tray 900 irmcf5 88q ty tape & reel 1000 irmcf588 q tr
irmcf588 2 www.irf.com ? 201 5 international rectifier f ebruary 20 , 201 5 table of contents 1 overview .................................................................................................................................................................... 5 2 pinout ......................................................................................................................................................................... 6 3 irmcf588 block diagr am and main function s .................................................................................................... 7 4 application connecti on and pin function .......................................................................................................... 9 4.1 8051 p eripheral i nterface g roup .................................................................................................................................. 11 4.2 m otion p eripheral i nterface g roup .............................................................................................................................. 12 4.3 a nalog i nterface g roup ............................................................................................................................................... 13 4.4 p ower i nterface g roup ................................................................................................................................................. 14 4.5 t est i nterface g roup .................................................................................................................................................... 14 4.6 f actory use g roup ........................................................................................................................................................ 14 5 dc characteristics .................................................................................................................................................. 15 5.1 a bsolute m aximum r atings .......................................................................................................................................... 15 5.2 s ystem c lock f requency and p ower c onsumption ......................................................................................................... 15 5.3 d igital i/o dc c haracteristics ...................................................................................................................................... 16 5.4 a nalog i/o dc c haracteristics ...................................................................................................................................... 1 7 5.5 a/d a ccuracy ............................................................................................................................................................... 17 5.5 u nder v oltage l ockout dc characteristics ................................................................................................................... 17 5.6 i trip comparator dc characteristics ............................................................................................................................. 18 5.7 aref c haracteristics .................................................................................................................................................... 18 6 ac characteristics .................................................................................................................................................. 19 6.1 d igital pll ac c haracteristics ...................................................................................................................................... 19 6.2 a nalog to d igital c onverter ac c haracteristics ........................................................................................................... 20 6.3 o p amp ac c haracteristics ............................................................................................................................................ 21 6.4 sync to svpwm and a/d c onversion ac t iming .......................................................................................................... 22 6.5 gatekill to svpwm ac t iming ................................................................................................................................... 23 6.6 i nternal o vercurrent trip ac t iming ............................................................................................................................ 23 6.7 i nterrupt ac t iming ...................................................................................................................................................... 24 6.8 i 2 c ac t iming ................................................................................................................................................................ 25 6.9 uart ac t iming ............................................................................................................................................................ 26 6.10 capture i nput ac t iming ......................................................................................................................................... 27 6.11 jtag ac t iming ......................................................................................................................................................... 28 7 i/o structure ........................................................................................................................................................... 29 8 pin list ....................................................................................................................................................................... 32 9 package dimensions ............................................................................................................................................... 35 10 part marking informa tion ............................................................................................................................... 36 11 qualification inform ation ............................................................................................................................... 36
irmcf588 3 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 list of tables table 1. analog channel sensing functions in leg and single shunt modes ............................................ 13 table 2. absolute maximum ratings ........................................................................................................ 15 table 3. system clock frequency .............................................................................................................. 15 table 4. digital i/o dc characteristics ...................................................................................................... 16 table 7. uvcc dc characteristics .............................................................................................................. 18 table 8. itrip dc characteristics ................................................................................................................ 18 table 9. cmext and aref dc characteristics ........................................................................................... 18 table 10. pll ac characteristics ............................................................................................................... 19 table 11 . a/d converter ac characteristics ............................................................................................ 20 table 12 current sensing op amp ac characteristics .............................................................................. 21 table 13. sync ac characteristics ............................................................................................................ 22 table 14. gatekill to svpwm ac timing ................................................................................................ 23 table 15. itrip ac timing ........................................................................................................................... 23 table 16. interrupt ac timing ................................................................................................................... 24 table 17. i2c ac timing ............................................................................................................................ 25 table 18. uart ac timing ......................................................................................................................... 26 table 19. capture ac timing .................................................................................................................. 27 table 20. jtag ac timing ......................................................................................................................... 28 table 21. pin list ....................................................................................................................................... 34
irmcf588 4 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 list of figures figure 1. typical application block diagram using irmcf588 .......................................... 5 figure 2. pinout of irmcf588 .......................................................................................... 6 figure 3. irmcf588 block diagram .................................................................................. 7 figure 4. irmcf588 single shunt connection diagram .................................................... 9 figure 5. irmcf588 analog front end diagram ............................................................. 10 figure 6. crystal circuit example .................................................................................... 19 figure 7. voltage droop and s/h hold time .................................................................... 20 figure 8. op amp output capacitor ................................................................................ 21 figure 9. sync timing ..................................................................................................... 22 figure 10. gatekill timing ............................................................................................... 23 figure 11. itrip timing ................................................................................................... 23 figure 12. interrupt timing ............................................................................................. 24 figure 13. i 2 c timing ...................................................................................................... 25 figure 14. uart timing .................................................................................................. 26 figure 15. capture timing ............................................................................................ 27 figure 16. jtag timing ................................................................................................... 28 figure 17. compressor, fan and pfc pwm outputs ....................................................... 29 figure 18. all digital i/o except pwm output ................................................................. 29 figure 19. reset, gatekill i/o ...................................................................................... 30 figure 20. analog input .................................................................................................. 30 figure 22 analog operational amplifier output and aref i/o structure ........................ 30 figure 23. vss,avss pin i/o structure ............................................................................ 31 figure 24. vdd,vddcap pin i/o structure ...................................................................... 31 figure 25. xtal0/xtal1 pins structure .......................................................................... 31
irmcf588 5 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 1 overview irmcf5 88 is a new generation international rectifier integrated circuit device primarily designed as a one - chip solution for complete two motor inverter ized appliance motor control applications. particular application includes a full dc inverter air conditioner which requires two motor sensorless control plus power factor control. unlike a traditional microcontroller or dsp, the irmc f588 provides a built - in t wo parallel running computation engines for two closed loop sensorless control algorithm using the unique flexible motion control engine (mce tm ) . the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmc f588 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic, while still supporting leg shunt current sensing. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upp er layer control tasks can be implemented in the 8051 high - speed 8 - bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging. figure 1 shows a typical application schematic using the irmc f588 in leg shunt mode. irmc f588 contains 64k bytes of flash program memory plus 16k bytes of otp memory and comes in a 100 - pin qfp package. emi filter irmcf588 pfc + 3-phase hvic driver ipm dc bus ac input (100- 230v) compressor motor spm 3-phase hvic driver outdoor fan 40-60w ir pfc+inverter ipm (iram630-1562f) 7 analog output digital i/o 5 12 21 temperature feedback analog actuators relay, valves, switches analog input rs232c serial comm (indoor unit) pwm 6 pwm fault ir uipm (irsm836-035ma) rs232c serial comm (mainnance) figure 1 . typical application block diagram using irmc f588
irmcf588 6 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 2 pinout p 1 . 1 / rxd 1 p 1 . 2 / txd 1 xtal 1 vss vddcap fs 2 p 4 . 5 / cap fpwmwh fpwmuh vss vddcap avss p 2 . 7 / aopwm 1 p 2 . 6 / aopwm 0 cpwmuh cpwmvh cpwmwh cpwmul cpwmvl cpwmwl ain 7 vss p 4 . 0 / itrip tck p 5 . 1 / tdi p 5 . 3 / tdo p 5 . 2 / tms p 4 . 3 p 3 . 0 pfcpwm vss fpwmvl ifbf 2 - ifbf 2 o ain 6 ipfco ipfc - ipfc + p 1 . 7 fpwmul fpwmvh fpwmwl ain 2 p 2 . 3 ifbc 2 o ain 1 vddcap vdd vdd ain 3 ain 4 ifbf 2 + ifbc 1 o p 1 . 0 / t 2 p 2 . 1 ifbc 1 - ifbf 1 + ifbf 1 - ifbf 1 o vdd 19 20 21 22 23 24 25 26 27 28 29 30 irmcf 588 ( top view ) 3 12 4 11 5 6 7 8 9 10 2 1 16 15 13 14 17 18 ain 0 p 2 . 5 p 4 . 7 / txd 2 p 1 . 5 p 2 . 2 fs 3 p 3 . 4 / t 0 fs 4 fs 3 fs 4 scl 57 56 55 54 53 52 51 73 64 72 65 71 70 69 68 67 66 74 75 60 61 63 62 59 58 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 ifbc 2 - ifbc 2 + ain 5 vss ifbc 1 + aref vpp vss p 3 . 1 / aopwm 2 p 3 . 7 p 3 . 6 p 4 . 1 / aopwm 3 p 4 . 2 / aopwm 4 pfcgkill cgatekill p4.4 p4.6/rxd2 reset xtal0 sda fs 1 fs 1 fs 2 p 3 . 2 / int 0 p 2 . 0 / nmi p 1 . 6 p 2 . 4 ain 8 ain9 figure 2 . pinout of irmc f588
irmcf588 7 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 3 irmc f588 block diagram and main functions irmc f588 block diagram for leg shunt mode is shown in figure 3 . compressor mce dual port ram 2 kbyte mce program ram 12 kbyte program flash 64 kb 8 b i t u p a d d r e s s / d a t a b u s adc s/h op amp d / a ( pwm ) timer counnter 0 , 1 , 2 watchdog timer uart i 2 c snd rcv 6 low loss svpwm cgatekill cpwm dual motion control engine monitoring host interface digital i / os 8 bit ( 8051 ) microcontroller jtag emulator debugger 4 freq synthesizer 2 ceramic resonator (4mhz) 30 mhz 3 capture interrupt control speed command port 1 scl sda port 2 port 3 pfc pwm 8 bit cpu core local ram 2 kbyte 120 mhz ifbc1 ifbc2 ifbf1 3 3 3 adcl pfcgkill pfc igbt adc s/h op amp low loss svpwm mce program ram 12 kbyte otp 16kb dual port ram 2 kbyte fan mce ipfc ain0-5 6 6 itrip fpwm ain6-9 4 ifbf2 3 to mce gpio port port 5 uart & i2c px.x d/a (pwm) aopwm 2 txd2/rxd2, scl/sca figure 3 . irmc f588 block diagram irmc f588 contains the following functions for sensorless ac motor control applications: motion control engine (mce tm ) ? sensorless foc (complete sensorless field oriented control) ? proportional plus integral block ? low pass filter ? differentiator and lag (high pass filter) ? ramp ? limit ? angle estimate (sensorless control) ? inverse clark transformation ? vector rotator ? bit latch ? peak detect ? transition ? multiply - divide (signed and unsigned) 8051 microcontroller ? two 16 bit timer/counters ? one 16 bit periodic timer ? one 16 bit watchdog timer ? one 16 bit capture timer ? up to 31 discrete digital i /os ? ten - channel 12 bit a/d o buffered (current sensing) three channels (0 ? 1.2v input) o unbuffered seven channels (0 ? 1.2v input) ? jtag port (4 pins) ? up to five channels of analog output (8 bit pwm) ? uart
irmcf588 8 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 ? i 2 c port ? dual mce tm control sequencer ? adder ? mce tm program memory (12 k byte x 2 ) ? divide (signed and unsigned) ? subtractor ? comparator ? counter ? accumulator ? switch ? shift ? atan (arc tangent) ? function block (any curve fitting, nonlinear function) ? 16 bit wide logic operations (and, or, xor, not, negate) ? 64k byte flash memory ? 2k byte data ram
irmcf588 9 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 4 application connection and pin function figure 4 shows the application connections in single shunt mode. figure 5 shows the a nalog front end diagram with a single shunt configuration . p 1.2/txd p1.1/rxd xtal 0 pwm signals 6 cgatekill ain 0,ain1,ain2, ain3, ain4, ain 5 uart (indoor unit) digital i/o control system clock 4mhz crystal p 2.6/aopwm0 analog output xtal 1 reset t di tclk tsm t do 0 .6v ifbc1+ ifbc1- ifbc1o other analog input 1.8v vdd 3.3v vss pfcpwm ip fc+ ipfc- ipfco ifbc 2+ ifbc2- ifbc2o p2.7/aopwm1 scl sda other communication (i 2 c) frequency synthesizer rs 232c i 2 c port 1 port 2 reset pwm 0 pwm 1 jtag interface low loss space vector pwm pfc pwm s /h s /h 8051 cpu dual port memory (2kb) & mce memory (12kb) compressor mce 12 bit a/d & mux system clock local ram (2kbyte) program flash (64kbyte) system reset watchdog timer timer s irmcf 588 pwm 2 p4.1 /aopwm3 port 3 vpp 6 1 .8v voltage regulator vddcap fan otp programming (6.5v) fan motor hvic 0 .6v current sensing ac 230v comp motor 12 bit a/d & mux mce memory (12kb) 0 .6v ifbf1+ ifbf1- ifbf1o ifb f2+ ifbf2- ifbf2o s /h s /h low loss space vector pwm fan mce current sensing ain 6,ain7,ain9, ain9 other analog input local ram (4kbyte) program otp (16kbyte) port 4 p 3.1/aopwm2 p4.2/aopwm4 pwm 3 pwm 4 port 5 analog output digital i/o control 4 hvic pwm signals 6 p4.0/itrip figure 4 . irmc f588 single shunt connection diagram
irmcf588 10 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 op amplifier op amplifier op amplifier comparators enable/disable digital filter enable/disable digital filter enable/disable op amplifier enable/disable a n a l o g m u l t i p l e x e r comparator 12bit a/d fan motor compressor motor p4.0/itrip ifbf2o ifbf2- ifbf2+ ifbf1o ifbf1- ifbf1+ cgatekill ifbc1o ifbc1+ ifbc1- ipfco ipfc+ ipfc- pfcgkil ain0 ain1 ain2 ain3 adcl ain5 0.6v 0.6v 0.6v 0.2v ac230v f/f f/f f/f set reset set reset set reset enable external gatekill enable external gatekill a n a l o g m u l t i p l e x e r 12bit a/d ain6 ain7 ain8 ain9 op amplifier ifbc2o ifbc2- ifbc2+ mce2 mce1 figure 5 . irmc f588 analog front end diagram
irmcf588 11 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 4.1 8051 peripheral interface group uart interface p1.2/txd output, channel 1 transmit data from irmc f588 p1.1/rxd input, channel 1 receive data to irmc f588 p4.6 / txd 2 output, channel 2 transmit data from irmc f588 p4.7 / rxd 2 input, channel 2 receive data to irmc f588 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer/counter 2 input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output p1.5 input/output port 1.5 p1.6 input/output port 1.6 p1.7 input/output port 1.6 p2.0/nmi input/output port 2.0, can be configured as non - maskable interrupt input p2.1 input/output port 2.1 p2.2 input/output port 2.2 p2.3 input/output port 2.3 p2.4 input/output port 2.4 p2.5 input/output port 2.5 p2.6/aopwm0 input/output port 2.6, can be configured as aopwm0 output p2.7/aopwm1 input/output port 2.7, can be configured as aopwm1 output p3.0 input/output port 3.0 p3.1/aopwm2 input/output port 3.1, can be configured as aopwm2 output p3.2/int0 input/output port 3.2, can be configured as int0 input p3.4/t0 input/output port 3.4, can be configured as t0 input for counter mode p 3.6 input/output port 3.6 p3.7 input/output port 3.7 p4.0/itrip input/output port 4.0, can be configured as overcurrent trip input for fan motor p4.1/aopwm3 input/output port 4.1, can be configured as aopwm3 analog output p4.2/aopwm4 input/output port 4.2, can be configured as aopwm4 analog output p4.3 input/output port 4.3 p4.4 input/output port 4.4 p4.5/cap input/output port 4.5 , can be configured as capture timer input p4.6/txd2 input/output port 4.6, can be configured as uart2 transmit p4.7/rxd2 input/output port 4.7, can be configured as uart2 receive p5.1/tdi input port 5.1, configured as jtag port by default p5.2/tms input port 5.2 , configured as jtag port by default p5.3/tdo output port 5.3, configured as jtag port by default analog output interface p2.6/aopwm0 input/output, can be configured as 8 - bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8 - bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configure d as 8 - bit pwm output 2 with programmable carrier frequency p4.1/aopwm3 input/output, can be configured as 8 - bit pwm output 3 with programmable carrier frequency p4.2/aopwm4 input/output, can be configured as 8 - bit pwm output with programmable carrier freq uency
irmcf588 12 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesn?t require external rc time constant i 2 c interface scl output, i 2 c clock output sda input/output, i 2 c data line 4.2 motion peripheral interface group pwm c pwmuh output, compressor motor pwm phase u high side gate signal, internally pulled down by 58k?, configured high true at a power up c pwmul output, compressor motor pwm phase u low side gate signal, i nternally pulled down by 58k?, configured high true at a power up c pwmvh output, compressor motor pwm phase v high side gate signal, internally pulled down by 58k?, configured high true at a power up c pwmvl output, compressor motor pwm phase v low side gat e signal, internally pulled down by 58k?, configured high true at a power up c pwmwh output, compressor motor pwm phase w high side gate signal, internally pulled down by 58k?, configured high true at a power up c pwmwl output, compressor motor pwm phase w low side gate signal, internally pulled down by 58k?, configured high true at a power up pfcpwm output, compressor motor pfcpwm output signal, internally pulled up by 70k?, configured low true at a power up f pwmuh output, fan motor pwm phase u high side g ate signal, internally pulled down by 58k?, configured high true at a power up f pwmul output, fan motor pwm phase u low side gate signal, internally pulled down by 58k?, configured high true at a power up f pwmvh output, fan motor pwm phase v high side gate signal, internally pulled down by 58k?, configured high true at a power up f pwmvl output, fan motor pwm phase v low side gate signal, internally pulled down by 58k?, configured high true at a power up f pwmwh output, fan motor pwm phase w high side gate si gnal, internally pulled down by 58k?, configured high true at a power up f pwmwl output, fan motor pwm phase w low side gate signal, internally pulled down by 58k?, configured high true at a power up fault c gatekill input, upon assertion this negates all six pwm signals, active low , internally pulled up by 70k? pfcgkill input, upon assertion, this negates pfcpwm signal, active low , internally pulled up by 70k? p4.0/itrip input/output port 4.0, can be configured as overcurrent trip input f or fan motor according to the setting of active_pol register , pulled up by 49kohm internal resistor
irmcf588 13 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) aref 0.6v buffered output ifbc 1 + input, operational amplifier positive input for compressor motor shunt sensing ifbc 1 - input, operational amplifie r negative input for compressor motor shunt sensing ifbc 1 o output, operational amplifier output for compressor motor shunt sensing ifbc2+ inpu t, operational amplifier positive input for compressor motor leg shunt sensing ifbc2 - input, operational amplifier negative input for compressor motor leg shunt sensing ifbc2o output, operational amplifier output for compressor motor leg shunt sensing ip fc + input, operational amplifier positive input for pfc current sensing ipfc - input, operational ampli fier negative input for pfc current sensing ipfc o output, operational amplifier output for pfc current sensing ifbf1+ input, operational amplifier positive input for fan motor shunt sensing ifbf1 - input, operational amplifier negative input for fan motor shunt sensing ifbf1o output, operational amplifier output for fan motor shunt sensing ifbf2+ input, operational amplifier positive input for fan mo tor leg shunt sensing ifbf2 - input, operational amplifier negative input for fan motor leg shunt sensing ifbf2o output, operational amplifier output for fan motor leg shunt sensing ain0 input, dc voltage sensing or analog input channel 0 (0 ? 1.2v), needs to be pulled down to avss if unused ain1 input , ac input voltage sensing or analog input channel 1 (0 ? 1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0 ? 1.2v), needs to be pulled down to avss if unused ain3 input, analog input channel 3 (0 ? 1.2v), needs to be pulled down to avss if unused ain 4 input, analog input channel 3 (0 ? 1.2v), needs to be pulled down to avss if unused a in5 input, analog input channel 5 (0 ? 1.2v), needs to be pulled down to avss if unused a in6 input, analog input channel 6 (0 ? 1.2v), associated with fan mce , needs to be pulled down to avss if unused ain7 input, analog input channel 7 (0 ? 1.2 v), associated with fan mce , needs to be pulled down to avss if unused ain8 input, analog input chan nel 8 (0 ? 1.2 v), associated with fan mce , needs to be pulled down to avss if unused ain9 input, analog input channel 9 (0 ? 1.2 v), associated with fan mce , needs to be pulled down to avss if unused analog channel leg shunt mode single shunt mode pin number(s) ipfc pfc current pfc current 27,28,29 ifbc 1 motor u phase current motor shunt current 19,20,21 ifbc2 motor v phase current - 6,7,8 ain1 ac voltage ac voltage 12 table 1 . analog channel sensing functions in leg and single shunt modes
irmcf588 14 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 4.4 power interface group vdd digital power (3.3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not designed to power a ny external circuits or devices. only capacitors should be connected to this pin. vss system common 4.5 test interface group p5.2/tms jtag test mode input or input digital port for compressor mce p5.3/ tdo jtag data output port for compressor mce p5.1/tdi jtag data input, or input digital port for compressor mce tck jtag test clock port for compressor mce 4.6 factory use group fs1 pin 82 and pin83 need to be connected and pulled up by 4.7 k resi s tor for factory purpose fs2 pin81 and pin84 need to be connected and pulled up by 4.7k resistor for factory purpose fs3 pin74 and pin75 need to be connected and pulled up by 4.7k resistor for factory purpose fs4 pin73 and pin72 need to be connected and pulled up by 4.7k resistor for factory purpose
irmcf588 15 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 5 dc characteristic s 5.1 absolute maximum ratings symbol parameter min typ max condition v dd supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 6.0 v respect to vss t a ambient temperature - 40 ?c - 85 ?c t s storage temperature - 65 ?c - 150 ?c table 2 . absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specif ications are not implied. 5.2 system clock frequency and power consumption c aref = 1nf, c mext = 100nf. vdd=3.3v, unless specified, ta = 25?c. symbol parameter min typ max unit sysclk system clock 32 - 1 2 0 mhz p d power consumption 1 5 0 1 - mw table 3 . system clock frequency note 1) the value is based on the condition of mce clock=1 0 0mhz, 8051 clock 20 mhz with an actual motor and pfc running by a typical mce application program and 8051 code.
irmcf588 16 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v il input low voltage - 0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 4 . digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl, sda pins. (3) applied to all digital i/o pins except scl and sda pins.
irmcf588 17 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 5.4 analog i/o dc c haracteristics - op amp s for compressor, fan and pfc current sensing c aref = 1nf . vdd =3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb - op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) v min min voltage for ain 0 - 9 60 mv na na (1) table 5 . analog i/o dc characteristics note: (1) data guaranteed by design. 5.5 a/d accuracy unless specified, ta = 25?c. a/d accuracy for current sensing ( ifb c1 +,ifb c1 - ,ifb c1 o, ifb c2 +,ifb c2 - ,ifb c2 o , ifb f1 +,ifb f1 - ,ifb f1 o, ifb f2 +,ifb f2 - ,ifb f2 o ,ipfc+,ipfc - ,ipfco ) , and analog input channels (ain0 - ain9) symbol parameter min typ max condition adc error error is the difference between ideal counts and compensated counts for any applied voltage in 0 - 1.2v range - 10counts - (1) table 5 . a/d accuracy note: (1) characterized not tested at manufacturing. 5.5 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 2.78 v 3.04 v 3. 2 3 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3. 2 3 v
irmcf588 18 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 uv cc h uvcc hysteresys - 73 mv - (1) table 6 . uvcc dc characteristics note: (1) data guaranteed by design. 5.6 itrip comparator dc characteristics unless specified, vdd =3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - v dd = 3.3 v itrip - itrip negative going threshold - 1.10v - v dd = 3.3 v itriph itrip hysteresys - 120mv - table 7 . itrip dc characteristics 5.7 aref chara cteristics c aref = 1nf. unless specified, ta = 25?c. symbol parameter min typ max condition v aref buffer output voltage - 600 mv - v vdd = 3.3 v ? v o load regulation (v dc - 0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 8 . cmext and aref dc characteristics note: (1) data guaranteed by design.
irmcf588 19 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6 ac c haracteristics 6.1 digital pll ac c haracteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 9 . pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m ? r 2 =1 k ? c 1 = 15 pf c 2 = 15 pf xtal0 xtal 1 figure 6 . crystal circuit example
irmcf588 20 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.2 analog to digital converter ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10 . a/d converter ac characteristics note: (1) data guaranteed by design. t h o l d v o l t a g e d r o o p t sampl e s / h v o l t a g e i n p u t v o l t a g e figure 7 . voltage droop and s/h hold time
irmcf588 21 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.3 op amp ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/sec - vdd = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 - (1) (2) t set settling time - 400 ns - vdd = 3.3 v, cl = 33 pf (1) table 11 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pf, see figure 8 . here typical op amp connection is show n but all op amp outputs sh ould be loaded with this capacitor value . avref irmcf588 ic external components 47pf figure 8 . op amp output capacitor
irmcf588 22 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.4 sync to svpwm and a/d conversion ac t iming sync iu,iv,iw t wsync t dsync1 ainx t dsync2 cpwmux,cpwmvx,cpwmwx t dsync3 figure 9 . sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - 9 - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 12. sync ac characteristics note: (1) only any 3 ainx from the compressor ain channels (ain0 - ain6) and any 2 ainx (ain7 - ain9) from the fan ain channels are converted once every sync events at the same time and the rest of the channels will be sampled once every 5 sync events.
irmcf588 23 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.5 gatekill to svpwm ac t iming cgatekill pwmux,pwmvx,pwmwx t wgk t dgk figure 10 . gatekill timing unless specified, ta = 25?c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 13. gatekill to svpwm ac timing 6.6 i nternal overcurrent trip ac t iming itrip cpwmuh , cpwmul , cpwmvh , cpwmvh , cpwmwh , cpwmwl fpwmuh , fpwmul , fpwmvh , fpwmvh , fpwmwh , fpwmwl t itrip figure 11 . itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 14. itrip ac timing
irmcf588 24 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.7 i nterrupt ac t iming p3. 2/int 0 internal program counter internal vector fetch t wint t dint figure 12 . interrupt timing unless specified, ta = 25?c. symbol parameter min typ max unit t wint int0, nmi interrupt assertion time 4 - - sysclk t dint int0, nmi latency - - 4 sysclk table 15. interrupt ac timing
irmcf588 25 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.8 i 2 c ac t iming scl sda t i2st1 t i2st 2 t i2wsetup t i2clk t i2 whold t i2 rsetup t i2rhold t i2clk t i2en1 t i2en 2 figure 13 . i 2 c timing unless specified, ta = 25?c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
irmcf588 26 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.9 uart ac t iming txd rxd data and parity bit start bit t baud stop bit t uartfil figure 14 . uart timing unless specified, ta = 25?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 17. uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
irmcf588 27 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.10 capture i nput ac t iming p 4 . 5 / cap crev ( h , l ) internal register t caphigh t capclk t crdelay t caplow t cldelay clast ( h , l ) internal register t intdelay interrupt vector fetch interrupt figure 15 . capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 18. capture ac timing
irmcf588 28 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 6.11 jtag ac t iming tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 16 . jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 19. jtag ac timing
irmcf588 29 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 7 i/o structure the following figure shows the pwm output ( c pwmuh/ c pwmul/ c pwmvh/ c pwmvl/ c pwmwh/ c pwmwl /pfcpwm /fpwmul/fpwmuh/fpwmvl/fpw mvh/fpwmwl/fpwmwh ) 270 ? 6.0v 6.0v internal digital circuit high true logic vdd1 (3.3v ) vss 58k ? pin figure 17 . compressor, fan and pfc pwm output s the following figure shows the digital i/o structure except the pwm output 6 . 0 v 6 . 0 v internal digital circuit low true logic vdd 1 ( 3 . 3 v ) 70 k ? pin vss 270 ? figure 18 . all digital i/o except pwm output
irmcf588 30 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 the following figure shows reset and c gatekill, pfcgkill i/o for structure. 270 ? 6 . 0 v 6 . 0 v reset gatekill circuit vdd 1 ( 3 . 3 v ) 70 k ? pin vss figure 19 . reset, gatekill i/o the following figure shows the analog input structure : 1 ? 6.0v 6.0v analog input pin avss analog circuit vddcap(1.8 v) figure 20 . analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit vddcap(1.8v) figure 21 analog operational amplifier output and aref i/o structure
irmcf588 31 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 the following figure shows the vss,avss pin i/o structure pin vdd avdd 6 . 0 v figure 22 . vss,avss pin i/o structure the following figure shows the vdd ,vddcap pin i/o structure pin vss 6 . 0 v figure 23 . vdd ,vddcap pin i/o structure the following figure shows the xtal0 and xtal1 pins structure 1 ? 6 . 0 v 6 . 0 v pin vss vddcap ( 1 . 8 v ) figure 24 . xtal0/xtal1 pins structure
irmcf588 32 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 8 pin list pin number pin name internal pull - up /pull - down pin type description 1 ifbf2 - i op amp positive input for 2 nd leg shunt resistor current sensing of fan motor, 0 - 1.2v range 2 p2.5 i/o discrete programmable i/o 3 p2.6/aopwm0 i/o discrete programmable i/o or pwm 0 digital output 4 p2.7/aopwm1 i/o discrete programmable i/o or pwm 1 digital output 5 ifbf1o o op amp output for 1 st leg or single shunt resistor current sensing of fan motor, 0 - 1.2v range 6 ifbc2o o op amp output 2 nd leg shunt current sensing of compressor motor , 0 - 1.2v range 7 ifbc2 - i op amp negative input 2 nd leg shunt current sensing of compressor motor , 0 - 1.2v range, needs to be pulled down to avss if unused 8 ifbc2 + i op amp positive input 2 nd leg shunt current sensing of compressor motor , 0 - 1.2v range, needs to be pulled down to avss if unused 9 ifbf1 - i op amp negative input for 1 st leg or single shunt resistor current sensing of fan motor, 0 - 1.2v range 10 ifbf1+ i op amp positive input for 1 st leg or single shunt resistor current sensing of fan motor, 0 - 1.2v range 11 ain0 i analog input channel (0 ? 1.2v) for dc voltage sensing , needs to be pulled down to avss if unused 12 ain1 i analog input channel 1, 0 - 1.2v range, for ac voltage sensing, needs to be pulled down to avss if unused 13 ain2 i analog input channel 2, 0 - 1.2v range, needs to be pulled down to avss if unused 14 ain3 i analog input channel 3, 0 - 1.2v range, needs to be pulled down to avss if unused 15 vddcap p internal 1.8v output, capacitor(s) to be connected 16 ain4 i analog input channel 4 , 0 - 1.2v range, needs to be pulled down to avss if unused 17 a in5 i analog input channel 5, 0 ? 1.2v range, needs to be pulled down to avss if unused 18 vdd p 3.3v digital power 19 ifbc - i op amp negative input for 1 st leg or single shunt current sensing of compressor motor , 0 - 1.2v range, needs to be pulled down to avss if unused 20 ifbc+ i op amp positive input for 1 st leg or single shunt current sensing of compressor motor , 0 - 1.2v range, needs to be pulled down to avss if unused 21 ifbco o op amp output for 1 st leg or single shunt current sensing of compressor motor , 0 - 1.2v range 22 vss p analog and digital c ommon 23 vss p analog and digital c ommon 24 vpp p otp programming voltage for fan mce 25 aref o analog reference voltage output (0.6v) 26 vss p analog and digital c ommon 27 ipfc - i op amp negative input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused
irmcf588 33 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 pin number pin name internal pull - up /pull - down pin type description 28 ipfc+ i op amp positive input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 29 ipfco o op amp output for application sensing , 0 - 1.2v range 30 avss p analog common 31 vddcap p internal 1.8v output, capacitor(s) to be connected 32 fpwmul 58 k pull down o pwm gate drive for phase u low side of fan motor , configurable either high or low true 33 fpwmvl 58 k pull down o pwm gate drive for phase v low side of fan motor , configurable either high or low true 34 fpwmwl 58 k pull down o pwm gate drive for phase w low side of fan motor , configurable either high or low true 35 vdd p 3.3v power 36 vss p analog and digital common 37 p3.1/aopwm2 i/o discrete programmable i/o or pwm 2 digital output 38 fpwmuh 58 k pull down o pwm gate drive for phase u high side of fan , configurable either high or low true 39 fpwmvh 58 k pull down o pwm gate drive for phase v high side of fan motor , configurable either high or low true. 40 fpwmwh 58 k pull down o pwm gate drive for phase w high side of fan motor , configurable either high or low true 41 c pwmwl 58 k pull down o pwm gate drive for phase w low side of compressor motor , configurable either high or low true. 42 c pwmvl 58 k pull down o pwm gate drive for phase v low side of compressor motor , configurable either high or low true 43 c pwmul 58 k pull down o pwm gate drive for phase u low side of compressor motor , configurable either high or low true 44 c pwmwh 58 k pull down o pwm gate drive for phase w high side of compressor motor , configurable either high or low true 45 p3.7 i/o discrete programmable i/o 46 p2.1 i/o discrete programmable i/o 47 p3.6 i/o discrete programmable i/o 48 p4.0/itrip 49 k pull up i/o discrete programmable i/o or fan motor overcurrent trip input, active low 49 p4.1/aopwm3 i/o di screte programmable i/o or pwm 3 digital output 50 p4.2/aopwm4 i/o di screte programmable i/o or pwm 4 digital output 51 c pwmvh 58 k pull down o pwm gate drive for phase v high side of compressor motor , configurable either high or low true 52 c pwmuh 58 k pull down o pwm gate drive for phase u high side of compressor motor , configurable either high or low true 53 p4.3 i/o discrete programmable i/o 54 p1.5 i/o discrete programmable i/o 55 pfcpwm i/o pfc pwm gate drive , configurable either high or low 56 pfcgkill 70 k pull up i pfcpwm shutdown input, active low input. 57 p4.4 i/o discrete programmable i/o 58 c gatekill 70 k pull up i pwm shutdown input, configurable digital filter, active low input. 59 p3.0 70 k pull up i/o discrete programmable i/o 60 p4.5/cap i/o discrete programmable i/o or capture timer input 61 p5.2/tms i jtag test mode select or digital input port 62 p4.6 / rxd2 i/o discrete programmable i/o , 2 nd uart receive
irmcf588 34 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 pin number pin name internal pull - up /pull - down pin type description 63 p5.3/ tdo o jtag test data output 64 p5.1/tdi i jtag test data input or digital input port 65 p4.7 / txd2 i/o discrete programmable i/o , 2 nd uart transmit 66 tck i jtag test clock 67 reset i reset, low true, schmitt trigger input 68 p1.1/rxd 1 i/o uart receiver input or discrete programmable i/o 69 vss p analog and digital common 70 p1. 2 / t xd 1 i/o uart transmitter output or discrete programmable i/o 71 p3.4/t0 i/o discrete programmable i/o or timer/counter 2 input 72 fs4 i/o factory use, need to be connected to pin73 73 fs4 i/o factory use, need to be connected to pin72 74 fs3 i/o factory use, need to be connected to pin75 75 fs3 i/o factory use, need to be connected to pin74 76 xtal0 i crystal input 77 xtal1 o crystal output 78 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 79 scl i/o i 2 c clock output (open drain, need pull up) 80 sda i/o i 2 c data (open drain, need pull up) 81 fs2 i/o factory use, need to be connected to pin84 82 fs1 i/o factory use, need to be connected to pin83 83 fs1 i /o factory use, need to be connected pin82 84 fs2 i/o factory use, need to be connected to pin81 85 ain9 i analog input channel (0 ? 1.2v), needs to be pulled down to avss if unused 86 ain8 i analog input channel (0 ? 1.2v), needs to be pulled down to avss if unused 87 p2.4 i/o discrete programmable i/o 88 p1.6 i/o discrete programmable i/o 8 9 p1.7 discrete programmable i/o 90 ain7 i analog input channel (0 ? 1.2v), needs to be pulled down to avss if unused 91 vdd p 3.3v digital power 92 ain6 i analog input channel (0 ? 1.2v 93 vss p digital common 94 vddcap p internal 1.8v output, capacitor(s) to be connected 95 p2.0/nmi i/o discrete programmable i/o or non - maskable interrupt input 96 p3.2/int0 i/o discrete programmable i/o or interrupt 0 input 97 p2.2 i/o discrete programmable i/o 98 p2.3 i/o discrete programmable i/o 99 ifb2o o op amp output for 2 nd leg shunt resistor current sensing of fan motor, 0 - 1.2v range 100 ifb2 - i op amp negative input for 2 nd leg shunt resistor current sensing of fan motor, 0 - 1.2v range table 20 . pin list
irmcf588 35 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 9 package dimensions
irmcf588 36 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 10 part marking information irmcf 588 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier part marking 11 qualification information qualification level industrial ?? (per jedec jesd 47e) moisture sensitivity level msl3 ??? (per ipc/jedec j - std - 020c) esd machine model class b (per jedec standard jesd22 - a114d) human body model class 2 (per eia/jedec standard eia/jesd22 - a115 - a) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information. note: test condition for temperature cycling test is - 40c to 125c. revision history
irmcf588 37 www.irf.com ? 201 5 international rectifier f ebruary 20,2015 data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information

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